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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. futu re routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am50dl128cg data sheet publication number 26880 revision a amendment +2 issue date november 7, 2002
preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 26880 rev: a amendment/ +2 issue date: november 7, 2002 refer to amd?s website (www.amd.com) for the latest information. am50dl128cg stacked multi-chip package (m cp) flash memory and sram two am29dl640g 64 megabit (4 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memories and 64 mbit (4 m x 16-bit) pseudo static ram with page mode distinctive characteristics mcp features power supply voltage of 2.7 to 3.3 volt high performance ? access time as fast as 70 ns package ? 88-ball fbga operating temperature ? ?40c to +85c flash memory features architectural advantages simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in another bank. ? zero latency between read and write operations flexible bank ? architecture ? read may occur in any of the three banks not being written or erased. ? four banks may be grouped by customer to achieve desired bank divisions. manufactured on 0.17 m process technology secsi? (secured silicon) sector: extra 256 byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. expressflash option allows entire sector to be available for factory-secured data ? customer lockable: sector is one-time programmable. once sector is locked, data cannot be changed. zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. boot sectors ? top and bottom boot sectors in the same device compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard performance characteristics high performance ? access time as fast as 70 ns ? program time: 4 s/word typical utilizing accelerate function ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode minimum 1 million write cycles guaranteed per sector 20 year data retention at 125 c ? reliable operation for the life of the system software features data management software (dms) ? amd-supplied software manages data programming, enabling eeprom emulation ? eases historical sector erase flash limitations supports common flash memory interface (cfi) program/erase suspend/erase resume ? suspends program/erase operations to allow programming/erasing in same bank data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features any combination of sectors can be erased ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode wp#/acc input pin ? write protect (wp#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status ? acceleration (acc) function accelerates program timing sector protection ? hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector ? temporary sector unprotect allows changing data in protected sectors in-system psram features power dissipation ? operating: 50 ma maximum ? standby: 100 a maximum ? deep power-down standby: 5 a ce1s# and ce2s chip select power down features using ce1s# and ce2s data retention supply voltage: 2.7 to 3.3 volt byte data control: lb#s (dq7?dq0), ub#s (dq15?dq8) 8-word page mode access
2 am50dl128cg november 7, 2002 preliminary general description am29dl640g features the am29dl640g is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. word mode data appears on dq15?dq0. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 70 or 85 ns and is offered in a 88-ball fbga package. standard control pins?chip enable (ce#f), write enable (we#), and output enable (oe#)?control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 mb banks with small and large sectors, and two 24 mb banks of large sectors only. sector addresses are fixed, system software can be used to form user-defined bank groups. during an erase/program operation, any of the three non-busy banks may be read from. note that only two banks can operate simultaneously. the device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the am29dl640g can be organized as both a top and bottom boot sector configuration. the secsi? (secured silicon) sector is an extra 256 byte sector capable of being permanently locked by amd or customers. the secsi indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, cus- tomer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secsi sector may store a secure, random 16 byte esn (electronic serial number), customer code (pro- grammed through amd?s expressflash service), or both. customer lockable parts may utilize the secsi sector as a one-time programmable area. dms (data management software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of eeprom devices. dms will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the flash memory device (or memory de- vices), and more. using dms, user-written software does not need to interface with the flash memory di- rectly. instead, the user's software accesses the flash memory by calling one of only six functions. amd pro- vides this software to simplify system design and soft- ware integration efforts. the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to the read mode. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly re- duced in both modes. bank megabits sector sizes bank 1 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword bank 2 24 mb forty-eight 64 kbyte/32 kword bank 3 24 mb forty-eight 64 kbyte/32 kword bank 4 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword
november 7, 2002 am50dl128cg 3 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 5 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 flash memory block diagram. . . . . . . . . . . . . . . . 6 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 special package handling instructions .................................... 7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 mcp device bus operations . . . . . . . . . . . . . . . . 10 table 1. device bus operations?flash word mode ..................... 11 flash device bus operations . . . . . . . . . . . . . . . 12 word configuration ................................................................. 12 requirements for reading array data ................................... 12 writing commands/command sequences ............................ 12 accelerated program operation .......................................... 12 autoselect functions ........................................................... 12 simultaneous read/write operations with zero latency ....... 12 standby mode ........................................................................ 12 automatic sleep mode ........................................................... 13 reset#: hardware reset pin ............................................... 13 output disable mode .............................................................. 13 table 2. am29dl640g sector architecture ....................................14 table 3. bank address ....................................................................17 table 4. secsi ? sector addresses ...............................................17 sector/sector block protection and unprotection .................. 18 table 5. am29dl640g boot sector/sector block addresses for pro- tection/unprotection ........................................................................18 write protect (wp#) ................................................................ 18 table 6. wp#/acc modes ..............................................................19 temporary sector unprotect .................................................. 19 figure 1. temporary sector unprotect operation........................... 19 figure 2. in-system sector protect/unprotect algorithms .............. 20 secsi? (secured silicon) sector flash memory region ............................................................ 21 figure 3. secsi sector protect verify.............................................. 22 hardware data protection ...................................................... 22 low v cc write inhibit ........................................................... 22 write pulse ?glitch? protection ............................................ 22 logical inhibit ...................................................................... 22 power-up write inhibit ......................................................... 22 common flash memory interface (cfi) . . . . . . . 22 table 7. cfi query identification string .......................................... 23 system interface string................................................................... 23 table 9. device geometry definition .............................................. 24 table 10. primary vendor-specific extended query ...................... 25 flash command definitions . . . . . . . . . . . . . . . . 26 reading array data ................................................................ 26 reset command ..................................................................... 26 autoselect command sequence ............................................ 26 enter secsi? sector/exit secsi sector command sequence .............................................................. 26 word program command sequence ..................................... 27 unlock bypass command sequence .................................. 27 figure 4. program operation .......................................................... 28 chip erase command sequence ........................................... 28 sector erase command sequence ........................................ 28 figure 5. erase operation............................................................... 29 erase suspend/erase resume comma nds ........................... 29 table 11. am29dl640g command definitions .............................. 30 flash write operation status . . . . . . . . . . . . . . . 31 dq7: data# polling ................................................................. 31 figure 6. data# polling algorithm .................................................. 31 ry/by#: ready/busy# ............................................................ 32 dq6: toggle bit i .................................................................... 32 figure 7. toggle bit algorithm........................................................ 32 dq2: toggle bit ii ................................................................... 33 reading toggle bits dq6/dq2 ............................................... 33 dq5: exceeded timing limits ................................................ 33 dq3: sector erase timer ....................................................... 33 table 12. write operation status ................................................... 34 absolute maximum ratings . . . . . . . . . . . . . . . . 35 figure 8. maximum negative overshoot waveform ...................... 35 figure 9. maximum positive overshoot waveform........................ 35 flash dc characteristics . . . . . . . . . . . . . . . . . . 36 cmos compatible .................................................................. 36 figure 10. i cc1 current vs. time (showing active and automatic sleep currents) ............................................................. 38 figure 11. typical i cc1 vs. frequency ............................................ 38 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. test setup.................................................................... 39 figure 13. input waveforms and measurement levels ................. 39 psram ac characteristics . . . . . . . . . . . . . . . . . 40 ce#s timing ........................................................................... 40 figure 14. timing diagram for alternating between pseudo sram to flash................................................... 40 read-only operations .................. ......................................... 41 figure 15. read operation timings ............................................... 41 hardware reset (reset#) .................................................... 42 figure 16. reset timings ............................................................... 42 erase and program operations .............................................. 43 figure 17. program operation timings.......................................... 44 figure 18. accelerated program timing diagram.......................... 44 figure 19. chip/sector erase operation timings .......................... 45 figure 20. back-to-back read/write cycle timings ...................... 46 figure 21. data# polling timings (during embedded algorithms). 46 figure 22. toggle bit timings (during embedded algorithms)...... 47 figure 23. dq2 vs. dq6................................................................. 47 temporary sector unprotect .................................................. 48 figure 24. temporary sector unprotect timing diagram .............. 48 figure 25. sector/sector block protect and unprotect timing diagram ............................................................. 49 alternate ce#f controlled erase and program operations .... 50 figure 26. flash alternate ce#f controlled write (erase/program) operation timings.......................................................................... 51 read cycle ............................................................................. 52 figure 27. pseudo sram read cycle........................................... 52 figure 28. page read timing ........................................................ 53 write cycle ............................................................................. 54 figure 29. pseudo sram write cycle?we# control ................... 54 figure 30. pseudo sram write cycle?ce1#s control ................ 55 figure 31. pseudo sram write cycle? ub#s and lb#s control.................................................................. 56 flash erase and programming performance . . 57 latchup characteristics . . . . . . . . . . . . . . . . . . . . 57 package pin capacitance. . . . . . . . . . . . . . . . . . . 57 flash data retention . . . . . . . . . . . . . . . . . . . . . . 57
4 am50dl128cg november 7, 2002 preliminary psram data retention . . . . . . . . . . . . . . . . . . . . . 58 psram power on and deep power down . . . . . 58 figure 32. deep power-down timing.............................................. 58 figure 33. power-on timing............................................................ 58 psram address skew . . . . . . . . . . . . . . . . . . . . . 59 figure 34. read address skew ...................................................... 59 figure 35. write address skew...................................................... 59 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 60 fta088?88-ball fine-pitch grid array 11.6 x 8 mm ............. 60 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 61
november 7, 2002 am50dl128cg 5 preliminary product selector guide mcp block diagram part number am50dl128cg speed options standard voltage range: v cc = 2.7?3.3 v flash memory pseudo sram 70 85 70 85 max access time, ns 70 85 70 85 page access time (psram), ns n/a n/a 30 35 ce#f access, ns 70 85 70 85 oe# access, ns 30 40 25 30 v ss v cc s reset#2 we# oe# ce1#ps lb# ub# ce#f1 wp#/acc ce2ps 64 mbit static ram 64 mbit flash memory #2 dq15 to dq0 dq15 to dq0 ry/by#1 v ss v cc f 64 mbit flash memory #1 a21 to a0 a21 to a0 a21 to a0 ce#f2 dq15 to dq0 v ss f v cc f ry/by#2 reset#1
6 am50dl128cg november 7, 2002 preliminary flash memory block diagram v cc v ss bank 1 address bank 2 address a21?a0 reset# we# ce# byte# dq15?dq0 wp#/acc state control & command register ry/by# bank 1 x-decoder oe# byte# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a0?a21 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 2 x-decoder y-gate bank 3 x-decoder bank 4 x-decoder y-gate bank 3 address bank 4 address
november 7, 2002 am50dl128cg 7 preliminary connection diagram special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, plcc, pdip, ssop). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. g3 g4 g5 g6 g7 g8 f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 b3 b4 b5 b6 b7 b8 nc nc nc ce#f2 ry/by#2 v ss nc a8 a11 we# wp#/acc lb# a7 nc a19 a12 ce2ps reset#1 ub# a6 a3 a9 a13 a20 ry/by#1 a18 a5 a2 a10 a14 nc nc a17 a4 a1 dq6 nc g9 f9 e9 d9 c9 b9 nc nc a15 a21 nc a16 nc nc dq1 v ss a0 m1 nc nc a1 g2 f2 e2 d2 c2 b2 m2 a2 m9 nc a9 nc m10 nc a10 nc nc nc h3 h4 h5 h6 h7 h8 dq13 dq15 h9 v cc f dq4 dq3 dq9 oe# ce#f1 h2 j3 j4 j5 j6 j7 j8 dq12 dq7 j9 v ss v cc ps v cc f dq10 dq0 ce#1fps j2 k3 k4 k5 k6 k7 k8 dq5 dq14 k9 nc nc dq11 dq2 dq8 nc k2 l3 l4 l5 l6 l7 l8 nc nc l9 nc nc v cc f v ss reset#2 nc l2 shared flash 1 only flash 2 only flash 1 and 2 shared sram only 88-ball fbga top view
8 am50dl128cg november 7, 2002 preliminary pin description a21?a0 = 22 address inputs (common) dq15?dq0 = 16 data inputs/outputs (common) ce#f1 = chip enable 1 (flash 1) ce#f2 = chip enable 2 (flash 2) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by#1 = ready/busy output (flash 1) ry/by#2 = ready/busy output (flash 2) ub# = upper byte control (psram) lb# = lower byte control (psram) reset#1 = hardware reset pin, active low (flash 1) reset#2 = hardware reset pin, active low (flash 2) wp#/acc = hardware write protect/ acceleration pin (flash) v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce#f1 oe# we# reset#1 ub# ry/by#1 wp#/acc lb# ce1#ps ce2ps ce#f2 reset#2 ry/by#2
november 7, 2002 am50dl128cg 9 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am50dl128 c g 70 i t tape and reel t = 7 inches s = 13 inches temperature range i = industrial (?40 c to +85 c) speed option see ?product selector guide? on page 5 flash process technology g = 0.17 m pseudo sram device density c = 64 mbits amd device number/description am50dl128cg stacked multi-chip package (mcp) flash memory and sram two am29dl640g 64 megabit (4 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memories and 64 mbit (4 m x 16-bit) pseudo static ram with page mode 88-ball fine pitch ball grid array, 11.6 x 8, 0.80 mm pitch package (fta088) valid combinations order number package marking am50dl128cg70i t, s m500000008 am50dl128cg85i t, s m500000009
10 am50dl128cg november 7, 2002 preliminary mcp device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. tables 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail.
november 7, 2002 am50dl128cg 11 preliminary table 1. device bus operations?flash word mode legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sadd = flash sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f1 or 2 = v il , ce1#s = v il and ce2s = v ih at the same time. 3. active flash is device being addressed. 4. don?t care or open lb#s or ub#s. 5. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 6. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 7. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection?. if wp#/acc = v hh, all sectors will be unprotected. 8. data will be retained in psram. 9. data will be lost in psram. 10. ce# inputs on both flash devices may be held low for this operation. 11. operation (notes 1, 2) ce#f active ce#f inactive ce1#ps ce2ps oe# we# addr. lb#s ub#s reset# wp#/ acc (note 5) dq7? dq0 dq15? dq8 (note 3) read from active flash (note 8) lh hh lh a in xx h l/h d out d out (note 9) h l write to active flash (note 8) lh hh hl a in xx h(note 5) d in d in (note 9) h l standby v cc 0.3 v hhxxx xx v cc 0.3 v h high-z high-z deep power-down standby v cc 0.3 v hlxxxxx v cc 0.3 v h high-z high-z output disable (note 10) l h l h hh x x x h l/h high-z high-z hh x x x flash hardware reset (note 8) x hh x x x x x l l/h high-z high-z (note 9) h l sector protect (notes 6, 10) (note 8) lh hh hl sadd, a6 = l, a1 = h, a0 = l xx v id l/h d in x (note 9) h l sector unprotect (notes 6, 10) (note 8) lh hh hl sadd, a6 = h, a1 = h, a0 = l xx v id (note 7) d in x (note 9) h l temporary sector unprotect (note 8) x hh xx x x x v id (note 7) d in high-z (note 9) h l read from psram h h l h l h a in ll hx d out d out h l high-z d out lh d out high-z write to psram h h l h x l a in ll hx d in d in h l high-z d in lh d in high-z
12 am50dl128cg november 7, 2002 preliminary flash device bus operations word configuration the device is in word configuration, dq15?dq0 are active and controlled by ce#f and oe#. requirements for reading array data to read array data from the outputs, the system must drive the ce#f and oe# pins to v il . ce#f is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to the flash read-only operations table for tim- ing specifications and to figure 15 for the timing dia- gram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce#f to v il , and oe# to v ih . for program operations, the ciof pin determines whether the device accepts program data in bytes or words. refer to ?flash device bus operations? for more information. the device features an unlock bypass mode to facil- itate faster programming. once a bank enters the un- lock bypass mode, only two write cycles are required to program a word or byte, instead of four. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. similarly, a ?sector address? is the address bits required to uniquely select a sector. the ?flash command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. the device address space is divided into four banks. a ?bank address? is the address bits required to uniquely select a bank. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the flash ac characteristics section contains timing specifica- tion tables and timing diagr ams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated pro- gramming, or device damage may result. in addition, the wp#/acc pin must not be left floating or uncon- nected; inconsistent behavior of the device may result . see ?write protect (wp#)? on page 18 for related in- formation. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the sector/sector block protection and unprotection and autoselect command se- quence sections for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 f and i cc7 f in the table represent the cur- rent specifications for read-while-program and read-while-erase, respectively. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#f and reset# pins are both held at v cc 0.3 v.
november 7, 2002 am50dl128cg 13 preliminary (note that this is a more restricted voltage range than v ih .) if ce#f and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the de- vice requires standard access time (t ce ) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 f in the table represents the standby current spec- ification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#f, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 f in the table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 f). if reset# is held at v il but not within v ss 0.3 v, the standby cur- rent will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not ex- ecuting (ry/by# pin is ?1?), the reset operation is com- pleted within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the psram ac characteristics tables for re- set# parameters and to figure 16 for the timing dia- gram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
14 am50dl128cg november 7, 2002 preliminary table 2. am29dl640g sector architecture bank sector sector address a21?a12 sector size (kbytes/kwords) (x16) address range bank 1 sa0 0000000000 8/4 00000h?00fffh sa1 0000000001 8/4 01000h?01fffh sa2 0000000010 8/4 02000h?02fffh sa3 0000000011 8/4 03000h?03fffh sa4 0000000100 8/4 04000h?04fffh sa5 0000000101 8/4 05000h?05fffh sa6 0000000110 8/4 06000h?06fffh sa7 0000000111 8/4 07000h?07fffh sa8 0000001xxx 64/32 08000h?0ffffh sa9 0000010xxx 64/32 10000h?17fffh sa10 0000011xxx 64/32 18000h?1ffffh sa11 0000100xxx 64/32 20000h?27fffh sa12 0000101xxx 64/32 28000h?2ffffh sa13 0000110xxx 64/32 30000h?37fffh sa14 0000111xxx 64/32 38000h?3ffffh sa15 0001000xxx 64/32 40000h?47fffh sa16 0001001xxx 64/32 48000h?4ffffh sa17 0001010xxx 64/32 50000h?57fffh sa18 0001011xxx 64/32 58000h?5ffffh sa19 0001100xxx 64/32 60000h?67fffh sa20 0001101xxx 64/32 68000h?6ffffh sa21 0001101xxx 64/32 70000h?77fffh sa22 0001111xxx 64/32 78000h?7ffffh
november 7, 2002 am50dl128cg 15 preliminary bank 2 sa23 0010000xxx 64/32 80000h?87fffh sa24 0010001xxx 64/32 88000h?8ffffh sa25 0010010xxx 64/32 90000h?97fffh sa26 0010011xxx 64/32 98000h?9ffffh sa27 0010100xxx 64/32 a0000h?a7fffh sa28 0010101xxx 64/32 a8000h?affffh sa29 0010110xxx 64/32 b0000h?b7fffh sa30 0010111xxx 64/32 b8000h?bffffh sa31 0011000xxx 64/32 c0000h?c7fffh sa32 0011001xxx 64/32 c8000h?cffffh sa33 0011010xxx 64/32 d0000h?d7fffh sa34 0011011xxx 64/32 d8000h?dffffh sa35 0011000xxx 64/32 e0000h?e7fffh sa36 0011101xxx 64/32 e8000h?effffh sa37 0011110xxx 64/32 f0000h?f7fffh sa38 0011111xxx 64/32 f 8000h?fffffh sa39 0100000xxx 64/32 f9000h?107fffh sa40 0100001xxx 64/32 108000h?10ffffh sa41 0100010xxx 64/32 110000h?117fffh sa42 0101011xxx 64/32 118000h?11ffffh sa43 0100100xxx 64/32 120000h?127fffh sa44 0100101xxx 64/32 128000h?12ffffh sa45 0100110xxx 64/32 130000h?137fffh sa46 0100111xxx 64/32 138000h?13ffffh sa47 0101000xxx 64/32 140000h?147fffh sa48 0101001xxx 64/32 148000h?14ffffh sa49 0101010xxx 64/32 150000h?157fffh sa50 0101011xxx 64/32 158000h?15ffffh sa51 0101100xxx 64/32 160000h?167fffh sa52 0101101xxx 64/32 168000h?16ffffh sa53 0101110xxx 64/32 170000h?177fffh sa54 0101111xxx 64/32 1 78000h?17ffffh sa55 0110000xxx 64/32 180000h?187fffh sa56 0110001xxx 64/32 188000h?18ffffh sa57 0110010xxx 64/32 190000h?197fffh sa58 0110011xxx 64/32 198000h?19ffffh sa59 0100100xxx 64/32 1a0000h?1a7fffh sa60 0110101xxx 64/32 1a8000h?1affffh sa61 0110110xxx 64/32 1b0000h?1b7fffh sa62 0110111xxx 64/32 1b8000h?1bffffh sa63 0111000xxx 64/32 1c0000h?1c7fffh sa64 0111001xxx 64/32 1c8000h?1cffffh sa65 0111010xxx 64/32 1d0000h?1d7fffh sa66 0111011xxx 64/32 1d8000h?1dffffh sa67 0111100xxx 64/32 1e0000h?1e7fffh sa68 0111101xxx 64/32 1e8000h?1effffh sa69 0111110xxx 64/32 1f0000h?1f7fffh sa70 0111111xxx 64/32 1f 8000h?1fffffh table 2. am29dl640g sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/kwords) (x16) address range
16 am50dl128cg november 7, 2002 preliminary bank 3 sa71 1000000xxx 64/32 200000h?207fffh sa72 1000001xxx 64/32 208000h?20ffffh sa73 1000010xxx 64/32 210000h?217fffh sa74 1000011xxx 64/32 218000h?21ffffh sa75 1000100xxx 64/32 220000h?227fffh sa76 1000101xxx 64/32 228000h?22ffffh sa77 1000110xxx 64/32 230000h?237fffh sa78 1000111xxx 64/32 238000h?23ffffh sa79 1001000xxx 64/32 240000h?247fffh sa80 1001001xxx 64/32 248000h?24ffffh sa81 1001010xxx 64/32 250000h?257fffh sa82 1001011xxx 64/32 258000h?25ffffh sa83 1001100xxx 64/32 260000h?267fffh sa84 1001101xxx 64/32 268000h?26ffffh sa85 1001110xxx 64/32 270000h?277fffh sa86 1001111xxx 64/32 2 78000h?27ffffh sa87 1010000xxx 64/32 280000h?28ffffh sa88 1010001xxx 64/32 288000h?28ffffh sa89 1010010xxx 64/32 290000h?297fffh sa90 1010011xxx 64/32 298000h?29ffffh sa91 1010100xxx 64/32 2a0000h?2a7fffh sa92 1010101xxx 64/32 2a8000h?2affffh sa93 1010110xxx 64/32 2b0000h?2b7fffh sa94 1010111xxx 64/32 2b8000h?2bffffh sa95 1011000xxx 64/32 2c0000h?2c7fffh sa96 1011001xxx 64/32 2c8000h?2cffffh sa97 1011010xxx 64/32 2d0000h?2d7fffh sa98 1011011xxx 64/32 2d8000h?2dffffh sa99 1011100xxx 64/32 2e0000h?2e7fffh sa100 1011101xxx 64/32 2e8000h?2effffh sa101 1011110xxx 64/32 2f0000h?2fffffh sa102 1011111xxx 64/32 2f 8000h?2fffffh sa103 1100000xxx 64/32 300000h?307fffh sa104 1100001xxx 64/32 308000h?30ffffh sa105 1100010xxx 64/32 310000h?317fffh sa106 1100011xxx 64/32 318000h?31ffffh sa107 1100100xxx 64/32 320000h?327fffh sa108 1100101xxx 64/32 328000h?32ffffh sa109 1100110xxx 64/32 330000h?337fffh sa110 1100111xxx 64/32 338000h?33ffffh sa111 1101000xxx 64/32 340000h?347fffh sa112 1101001xxx 64/32 348000h?34ffffh sa113 1101010xxx 64/32 350000h?357fffh sa114 1101011xxx 64/32 358000h?35ffffh sa115 1101100xxx 64/32 360000h?367fffh sa116 1101101xxx 64/32 368000h?36ffffh sa117 1101110xxx 64/32 370000h?377fffh sa118 1101111xxx 64/32 3 78000h?37ffffh table 2. am29dl640g sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/kwords) (x16) address range
november 7, 2002 am50dl128cg 17 preliminary note: the address range is a21:a0. table 3. bank address table 4. secsi ? sector addresses bank 4 sa119 1110000xxx 64/32 380000h?387fffh sa120 1110001xxx 64/32 388000h?38ffffh sa121 1110010xxx 64/32 390000h?397fffh sa122 1110011xxx 64/32 398000h?39ffffh sa123 1110100xxx 64/32 3a0000h?3a7fffh sa124 1110101xxx 64/32 3a8000h?3affffh sa125 1110110xxx 64/32 3b0000h?3b7fffh sa126 1110111xxx 64/32 3b8000h?3bffffh sa127 1111000xxx 64/32 3c0000h?3c7fffh sa128 1111001xxx 64/32 3c8000h?3cffffh sa129 1111010xxx 64/32 3d0000h?3d7fffh sa130 1111011xxx 64/32 3d8000h?3dffffh sa131 1111 100xxx 64/32 3e0000h?3e7fffh sa132 1111 101xxx 64/32 3e8000h?3effffh sa133 1111110xxx 64/32 3f 0000h?3f7fffh sa134 111111 1000 8/4 3f8000h?3f8fffh sa135 111111 1001 8/4 3f9000h?3f9fffh sa136 111111 1010 8/4 3fa000h?3fafffh sa137 1111111011 8/4 3fb 000h?3fbfffh sa138 1111111100 8/4 3fc 000h?3fcfffh sa139 1111111101 8/4 3fd 000h?3fdfffh sa140 1111111110 8/4 3fe 000h?3fefffh sa141 1111111111 8/4 3ff 000h?3fffffh bank a21?a19 1 000 2 001, 010, 011 3 100, 101, 110 4 111 device sector size (x8) address range (x16) address range am29dl640g 256 bytes 000000h?0000ffh 00000h?0007fh table 2. am29dl640g sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/kwords) (x16) address range
18 am50dl128cg november 7, 2002 preliminary sector/sector block protection and unprotection (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table 5). the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. sector protection/unprotection can be imple- mented via two methods. table 5. am29dl640g boot sector/sector block addresses for protection/unprotection sector protection/ unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 25 shows the timing diagram. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro- tect write cycle. note that the sector unprotect algo- rithm unprotects all sectors in parallel. all previously protected sectors must be individually re-protected. to change data in protected sectors efficiently, the tem- porary sector unprotect function is available. see ?temporary sector unprotect?. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see the sector/sector block protection and unprotection section for details. write protect (wp#) the write protect function provides a hardware method of protecting without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in ?sector/sector block protection and unprotection?. sector a21?a12 sector/ sector block size sa0 0000000000 8 kbytes sa1 0000000001 8 kbytes sa2 0000000010 8 kbytes sa3 0000000011 8 kbytes sa4 0000000100 8 kbytes sa5 0000000101 8 kbytes sa6 0000000110 8 kbytes sa7 0000000111 8 kbytes sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) kbytes sa11?sa14 00001xxxxx 256 (4x64) kbytes sa15?sa18 00010xxxxx 256 (4x64) kbytes sa19?sa22 00011xxxxx 256 (4x64) kbytes sa23?sa26 00100xxxxx 256 (4x64) kbytes sa27-sa30 00101xxxxx 256 (4x64) kbytes sa31-sa34 00110xxxxx 256 (4x64) kbytes sa35-sa38 00111xxxxx 256 (4x64) kbytes sa39-sa42 01000xxxxx 256 (4x64) kbytes sa43-sa46 01001xxxxx 256 (4x64) kbytes sa47-sa50 01010xxxxx 256 (4x64) kbytes sa51-sa54 01011xxxxx 256 (4x64) kbytes sa55?sa58 01100xxxxx 256 (4x64) kbytes sa59?sa62 01101xxxxx 256 (4x64) kbytes sa63?sa66 01110xxxxx 256 (4x64) kbytes sa67?sa70 01111xxxxx 256 (4x64) kbytes sa71?sa74 10000xxxxx 256 (4x64) kbytes sa75?sa78 10001xxxxx 256 (4x64) kbytes sa79?sa82 10010xxxxx 256 (4x64) kbytes sa83?sa86 10011xxxxx 256 (4x64) kbytes sa87?sa90 10100xxxxx 256 (4x64) kbytes sa91?sa94 10101xxxxx 256 (4x64) kbytes sa95?sa98 10110xxxxx 256 (4x64) kbytes sa99?sa102 10111xxxxx 256 (4x64) kbytes sa103?sa106 11000xxxxx 256 (4x64) kbytes sa107?sa110 11001xxxxx 256 (4x64) kbytes sa111?sa114 11010xxxxx 256 (4x64) kbytes sa115?sa118 11011xxxxx 256 (4x64) kbytes sa119?sa122 11100xxxxx 256 (4x64) kbytes sa123?sa126 11101xxxxx 256 (4x64) kbytes sa127?sa130 11110xxxxx 256 (4x64) kbytes sa131?sa133 1111 100xxx, 1111 101xxx, 1111110xxx 192 (3x64) kbytes sa134 1111111000 8 kbytes sa135 1111111001 8 kbytes sa136 1111111010 8 kbytes sa137 1111111011 8 kbytes sa138 1111111100 8 kbytes sa139 1111111101 8 kbytes sa140 1111111101 8 kbytes sa141 1111111111 8 kbytes sector a21?a12 sector/ sector block size
november 7, 2002 am50dl128cg 19 preliminary if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors de- pends on whether they were last protected or unpro- tected using the method described in ?sector/sector block protection and unprotection?. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. table 6. wp#/acc modes temporary sector unprotect (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table 5). this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 1 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. if the wp#/acc pin is at v il , sectors 0, 1, 140, and 141 will remain protected during the temporary sector unprotect mode. figure 1. temporary sector unprotect operation wp# input voltage device mode v il disables programming and erasing in sa0, sa1, sa140, and sa141 v ih enables programming and erasing in sa0, sa1, sa140, and sa141 v hh enables accelerated programming (acc). see ?accelerated program operation? on page 12. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 140, and 141 will remain protected). 2. all previously protected sectors are protected once again.
20 am50dl128cg november 7, 2002 preliminary figure 2. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
november 7, 2002 am50dl128cg 21 preliminary secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. the customer-lock- able version has the secsi (secured silicon) sector indicator bit permanently set to a ?0.? thus, the secsi sector indicator bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. the system accesses the secsi sector secure through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence?). after the system has written the enter secsi sector com- mand sequence, it may read the secsi sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command se- quence, or until power is removed from the device. on power-up, or following a hardware reset, the device re- verts to sending commands to the first 256 bytes of sector 0. note that the acc function and unlock by- pass modes are not available when the secsi sector is enabled. factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is pro- tected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is preprogrammed with both a random number and a secure esn. the 8-word random number will at addresses 000000h?000007h in word mode (or 000000h?00000fh in byte mode). the secure esn will be programmed in the next 8 words at addresses 000008h?00000fh (or 000010h?000020h in byte mode). the device is available preprogrammed with one of the following: a random, secure esn only customer code through the expressflash service both a random, secure esn and customer code through the expressflash service. customers may opt to have their code programmed by amd through the amd expressflash service. amd programs the customer?s code, with or without the ran- dom esn. the devices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s expressflash service. customer lockable: secsi sector not programmed or protect ed at the factory if the security feature is not required, the secsi sector can be treated as an additional flash memory space. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secsi sector. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector re- gion without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region com- mand sequence to return to reading and writing the remainder of the array. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way.
22 am50dl128cg november 7, 2002 preliminary . figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 11 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce#f or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce#f = v ih or we# = v ih . to initiate a write cycle, ce#f and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce#f = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 7?10. to terminate reading cfi data, the system must write the reset command.the cfi query mode is not accessible when the device is exe- cuting an embedded program or embedded erase al- gorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 7?10. the system must write the reset command to return the de- vice to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. al- ternatively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
november 7, 2002 am50dl128cg 23 preliminary table 7. cfi query id entification string table 8. system interface string addresses (word mode) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (word mode) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
24 am50dl128cg november 7, 2002 preliminary table 9. device geometry definition addresses (word mode) data description 27h 0017h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 007dh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
november 7, 2002 am50dl128cg 25 preliminary table 10. primary vendor-specific extended query addresses (word mode) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 0004h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 0077h simultaneous operation 00 = not supported, x = number of sectors (excluding bank 1) 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 01h = 8 x 8 kbyte sectors, top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0017h bank 1 region information x = number of sectors in bank 1 59h 0030h bank 2 region information x = number of sectors in bank 2 5ah 0030h bank 3 region information x = number of sectors in bank 3 5bh 0017h bank 4 region information x = number of sectors in bank 4
26 am50dl128cg november 7, 2002 preliminary flash command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 11 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#f, whichever happens later. all data is latched on the rising edge of we# or ce#f, whichever hap- pens first. refer to the psram ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same excep- tion. see the erase suspend/erase resume com- mands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the section for more information. the flash read-only operations table provides the read parameters, and figure 15 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to the read mode. once erasure be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. once programming begins, how- ever, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a pr ogram or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autose- lect mode. the system may read any number of autoselect codes without reinitiating the command se- quence. table 11 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate bank address (ba) and sector address (sadd). table 2 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, sixteen-byte electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi
november 7, 2002 am50dl128cg 27 preliminary sector command sequence. the device continues to access the secsi sector region until the system is- sues the four-cycle exit secsi sector command se- quence. the exit secsi sector command sequence returns the device to normal operation. the secsi sector is not accessible when the device is executing an embedded program or embedded erase algorithm. table 11 shows the address and data requirements for both command sequences. see also ?secsi? (se- cured silicon) sector flash memory region? for further information. note that the acc function and unlock by- pass modes are not available when the secsi sector is enabled. word program command sequence the system may program the device by word. pro- gramming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algo- rithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 11 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to the flash write oper- ation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. note that the secsi sector, autoselect, and cfi functions are unavailable when a program opera- tion is in progress. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 11 shows the require- ments for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (see table 11). the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 4 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
28 am50dl128cg november 7, 2002 preliminary figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 11 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the flash write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. note that the secsi sector, autoselect, and cfi functions are unavailable when a program op- eration is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 11 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 80 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 80 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. note that the secsi sector, autoselect, and cfi func- tions are unavailable when a program operation is in progress. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can de- start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 11 for program command sequence.
november 7, 2002 am50dl128cg 29 preliminary termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the flash write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. figure 5. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the flash write operation status section for information on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the flash write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the au- toselect mode, the device reverts to the erase sus- pend mode, and is ready for another valid operation. refer to the sector/sector block protection and un- protection and autoselect command sequence sec- tions for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-sus- pended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 11 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
30 am50dl128cg november 7, 2002 preliminary table 11. am29dl640g command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce#f pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce#f pulse, whichever happens first. sadd = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. refer to table 2 for information on sector addresses. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. address bits a21?a19 select a bank. refer to table 3 for information on sector addresses. notes: 1. see tables 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a12 are don?t cares for unlock and command cycles, unless sadd or pa is required. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id, device id, or secsi sector factory protect information. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read across the fourth, fifth, and sixth cycles. 10. the data is 80h for factory locked and 00h for not factory locked. 11. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 device id (note 9) word 6 555 aa 2aa 55 (ba)555 90 (ba)x01 7e (ba)x0e 02 (ba)x0f 01 secsi sector factory protect (note 10) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 80/00 sector/sector block protect verify (note 11) word 4 555 aa 2aa 55 (ba)555 90 (sadd) x02 00/01 enter secsi sector region word 3 555 aa 2aa 55 555 88 exit secsi sector region word 4 555 aa 2aa 55 555 90 xxx 00 program word 4 555 aa 2aa 55 555 a0 pa pd unlock bypass word 3 555 aa 2aa 55 555 20 unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sadd 30 erase suspend (note 14) 1 ba b0 erase resume (note 15) 1 ba 30 cfi query (note 16) word 1 55 98
november 7, 2002 am50dl128cg 31 preliminary flash write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 12 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase sus- pend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 (or dq7?dq0 for byte mode) on the fol- lowing read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq15?dq8 (dq7?dq0 in byte mode) while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 (or dq7?dq0 for byte mode) will appear on successive read cycles. table 12 shows the outputs for data# polling on dq7. figure 6 shows the data# polling algorithm. figure 21 in the psram ac characteristics section shows the data# polling timing diagram. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
32 am50dl128cg november 7, 2002 preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-sus- pend-read mode. table 12 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce#f to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# poll- ing). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 12 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 22 in the ?flash ac characteristics? section shows the tog- gle bit timing diagrams. figure 23 shows the differ- ences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 7. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
november 7, 2002 am50dl128cg 33 preliminary dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce#f to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 12 to compare out- puts for dq2 and dq6. figure 7 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 23 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq15?dq0 (or dq7?dq0 for byte mode) at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the pro- gram or erase operation. the system can read array data on dq15?dq0 (or dq7?dq0 for byte mode) on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 7). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 12 shows the status of dq3 relative to the other status bits.
34 am50dl128cg november 7, 2002 preliminary table 12. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
november 7, 2002 am50dl128cg 35 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?55 c to +125 c ambient temperature with power applied . . . . . . . . . . . . . . ?40 c to +85 c voltage with respect to ground v cc f, v cc s (note 1) . . . . . . . . . . . . ?0.5 v to +4.0 v reset# (note 2) . . . . . . . . . . . .?0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9. 2. minimum dc input voltage on pins reset#, and wp#/acc is ?0.5 v. during voltage transitions, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8. maximum dc input voltage on pin reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc f/v cc s supply voltages v cc f/v cc s for standard voltage range . . 2.7 v to 3.3 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
36 am50dl128cg november 7, 2002 preliminary notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. 6. ce#f refers to chip enable input of active flash (device being addressed). flash dc characteristics cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit reset# input load current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i lr reset leakage current v cc = v cc max = 12.5 v 35 a i lia acc input leakage current v cc = v cc max , wp#/acc = v acc max 35 a i cc1 f flash v cc active read current (notes 1, 2) ce#f = v il , oe# = v ih , word mode 5 mhz 10 16 ma 1 mhz 2 4 i cc2 f flash v cc active write current (notes 2, 3) ce#f = v il , oe# = v ih , we# = v il 15 30 ma i cc3 f flash v cc standby current (note 2) v cc f = v cc max , ce#f, reset#, wp#/acc = v cc f 0.3 v 0.2 5 a i cc4 f flash v cc reset current (note 2) v cc f = v cc max , reset# = v ss 0.3 v, wp#/acc = v cc f 0.3 v 0.2 5 a i cc5 f flash v cc current automatic sleep mode (notes 2, 4) v cc f = v cc max , v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 f flash v cc active read-while-program current (notes 1, 2) ce#f = v il , oe# = v ih word 21 45 ma i cc7 f flash v cc active read-while-erase current (notes 1, 2) ce#f = v il , oe# = v ih word 21 45 ma i cc8 f flash v cc active program-while-erase-suspended current (notes 2, 5) ce#f = v il , oe#f = v ih 17 35 ma v il input low voltage ?0.2 0.8 v v ih input high voltage 2.4 v cc + 0.2 v v hh voltage for wp#/acc program acceleration and sector protection/unprotection 8.5 9.5 v v id voltage for sector protection, autoselect and temporary sector unprotect 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc f = v cc s = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc f = v cc s = v cc min 0.85 x v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko flash low v cc lock-out voltage (note 5) 2.3 2.5 v
november 7, 2002 am50dl128cg 37 preliminary psram dc & operating characteristics notes: 1. v cc ? 1.0 v for a 10 ns pulse width. 2. v cc + 1.0 v for a 10 ns pulse width. parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ?1.0 1.0 a i lo output leakage current ce1#s = v ih , ce2s = v il or oe# = v ih or we# = v il , v io = v ss to v cc ?1.0 1.0 a i cc operating power supply current i io = 0 ma, ce1#s = v il , ce2s = v ih , v in = v ih or v il 2ma i cc1 s operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih , t rc = min. 50 ma i cc2 s page access operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih , t pc = min. 25 ma v ol output low voltage i ol = 1.0 ma 0.4 v v oh output high voltage i oh = ?0.5 ma 2 v i sb standby current (cmos) ce#1 = v ccs ? 0.2 v, ce2 = v ccs ? 0.2 v 100 a i dsb deep power-down standby ce2 = 0.2 v 5 a v il input low voltage ?0.3 (note 1) 0.4 v v ih input high voltage 2.4 v cc + 0.3 (note 2) v
38 am50dl128cg november 7, 2002 preliminary flash dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 11. typical i cc1 vs. frequency 2.7 v 3.3 v 4 6 12
november 7, 2002 am50dl128cg 39 preliminary test conditions table 13. test specifications key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition 70, 85 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 13. input waveforms and measurement levels
40 am50dl128cg november 7, 2002 preliminary psram ac characteristics ce#s timing figure 14. timing diagram for alternating between pseudo sram to flash parameter description test setup all speeds unit jedec std ?t ccr ce#s recover time ? min 0 ns ce#f t ccr t ccr ce1#s ce2s t ccr t ccr
november 7, 2002 am50dl128cg 41 preliminary flash ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications 3. measurements performed by placing a 50 ? termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . note: ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 15. read operation timings parameter description test setup speed jedec std. 70 85 unit t avav t rc read cycle time (note 1) min 70 85 ns t avqv t acc address to output delay ce#f, oe# = v il max 70 85 ns t elqv t ce chip enable to output delay oe# = v il max 70 85 ns t glqv t oe output enable to output delay max 30 40 ns t ehqz t df chip enable to output high z (notes 1, 3) max 30 35 ns t ghqz t df output enable to output high z (notes 1, 3) max 30 ns t axqx t oh output hold time from addresses, ce#f or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce#f oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
42 am50dl128cg november 7, 2002 preliminary flash ac characteristics hardware reset (reset#) note: not 100% tested. note: ce#f refers to the flash device being reset (either ce#f1 or ce#f2). figure 16. reset timings parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset#1, reset#2 ry/by#1, ry/by#2 ry/by#1, ry/by#2 t rp t ready reset timings not during embedded algorithms t ready ce#f, oe# t rh ce#f, oe# reset timings during embedded algorithms reset#1, reset#2 t rp t rb
november 7, 2002 am50dl128cg 43 preliminary flash ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. 3. ce#f refers to chip enable input of active flash (device being addressed). parameter speed jedec std description 70 85 unit t avav t wc write cycle time (note 1) min 70 85 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 40 45 ns t aht address hold time from ce#f or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 40 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time (ce#f to we#) min 0 ns t elwl t cs ce#f setup time min 0 ns t ehwh t wh we# hold time (ce#f to we#) min 0 ns t wheh t ch ce#f hold time min 0 ns t wlwh t wp write pulse width min 30 35 ns t whdl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) word typ 7 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
44 am50dl128cg november 7, 2002 preliminary flash ac characteristics oe# we# ce#f v cc f data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. 3 . ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 17. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
november 7, 2002 am50dl128cg 45 preliminary flash ac characteristics oe# ce#f addresses v cc f we# data 2aah sadd t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sadd = sector address (for sector erase), va = valid address for reading status data (see ?flash write operation status?. 2 . these waveforms are for the word mode. 3 . ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 19. chip/sector erase operation timings
46 am50dl128cg november 7, 2002 preliminary flash ac characteristics oe# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce#f controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w ce#f note: ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 20. back-to-back read/write cycle timings we# ce#f oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc notes: 1. va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 21. data# polling timings (during embedded algorithms)
november 7, 2002 am50dl128cg 47 preliminary flash ac characteristics oe# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# ce#f note: 1. va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 22. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce#f to toggle dq2 and dq6. figure 23. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
48 am50dl128cg november 7, 2002 preliminary flash ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce#f we# ry/by# t vidr t rsp program or erase command sequence t rrb note: ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 24. temporary sector unprotect timing diagram
november 7, 2002 am50dl128cg 49 preliminary flash ac characteristics sector/sector block protect: 150 s, sector/sector block unprotect: 15 ms 1 s reset# sadd, a6, a1, a0 data ce#f we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0, sadd = sector address. note: ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash device must be held high during this operation. figure 25. sector/sector block protect and unprotect timing diagram
50 am50dl128cg november 7, 2002 preliminary flash ac characteristics alternate ce#f controlled erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. 3. ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). parameter speed jedec std description 70 85 unit t avav t wc write cycle time (note 1) min 70 85 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 40 45 ns t dveh t ds data setup time min 40 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce#f pulse width min 40 45 ns t ehel t cph ce#f pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
november 7, 2002 am50dl128cg 51 preliminary flash ac characteristics t ghel t ws oe# ce#f we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sadd for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sadd = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. ce#f refers to active flash device being addressed (either ce#f1 or ce#f2). the chip enable input of the inactive flash devic e must be held high during this operation. 5. waveforms are for the word mode. figure 26. flash alternate ce#f controll ed write (erase/program) operation timings
52 am50dl128cg november 7, 2002 preliminary psram ac characteristics read cycle notes: 1. t od, t odo , t bd , and t odw are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. if ce#, lb#, or ub# goes low at the same time or before we# goes high, the outputs will remain at high impedance. 3. if ce#, lb#, or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. figure 27. pseudo sram read cycle parameter symbol description speed unit 70 85 t rc read cycle time min 70 85 ns t acc address access time max 70 85 ns t co chip enable access time max 70 85 ns t oe output enable access time max 25 ns t ba data byte control access time max 25 ns t coe chip enable low to output active min 10 ns t oee output enable low to output active min 0 ns t be data byte control low to output active min 0 ns t od chip enable high to output high-z max 20 ns t odo output enable high to output high-z max 20 ns t bd data byte control high to output high-z max 20 ns t oh output data hold from address change min 10 ns t pm page mode time min 70 ns t pc page mode cycle time min 30 ns t aa page mode address access time max 30 ns t aoh page output data hold time min 10 ns t rc t acc addresses a20 to a0 ce#1 ce2 oe# we# lb#, ub# d out dq15 to dq0 t co t oh fixed high high-z high-z t oe t ba t od t odo t bd valid data out indeterminate t be t oee t coe
november 7, 2002 am50dl128cg 53 preliminary psram ac characteristics notes: 1. t od, t odo , t bd , and t odw are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. if ce#, lb#, or ub# goes low at the same time or before we# goes high, the outputs will remain at high impedance. 3. if ce#, lb#, or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. figure 28. page read timing addresses a2 to a0 addresses a20 to a3 ce#1 ce2 oe# we# lb#, ub# d out dq15 to dq0 t pm t rc t pc t pc t ba t oe t be t coe t aa t od t co t bd t acc t oee t pc d out d out d out d out t aa t aa t odo t oh t aoh t aoh t aoh fixed high maximum 8 words
54 am50dl128cg november 7, 2002 preliminary psram ac characteristics write cycle notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. 3. if ce#1s, lb# or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. 4. if ce#1s, lb# or ub# goes high at the same time or before we# goes high, the outputs will remain at high impedance. figure 29. pseudo sram write cycle?we# control parameter symbol description speed unit 70 85 t wc write cycle time min 70 85 ns t wp write pulse time min 50 60 ns t cw chip enable to end of write min 60 70 ns t bw data byte control to end of write min 60 70 ns t as address setup time min 0 ns t wr write recovery time min 0 ns t odw we# low to write to output high-z max 20 ns t oew we# high to write to output active min 0 ns t ds data set-up time min 30 t dh data hold from write time min 0 ns t ch ce2 hold time min 300 s t wc t wp t wr t cw t bw valid data in t as t ch t oew addresses a20 to a0 we# ce#1 ce2 lb#, ub# d in dq15 to dq0 d out dq15 to dqo t odw t ds t dh high-z (note 1) (note 3) (note 4)
november 7, 2002 am50dl128cg 55 preliminary psram ac characteristics notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. figure 30. pseudo sram write cycle?ce1#s control t wc valid data in t as t ch addresses a20 to a0 ce#1 ce2 we# lb#, ub# d in dq15 to dq0 d out dq15 to dq0 t cw t ds t dh t wp t wr t bw t be t odw t coe high-z high-z (note 1) (note 1)
56 am50dl128cg november 7, 2002 preliminary psram ac characteristics notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. figure 31. pseudo sram write cycle? ub#s and lb#s control t wc valid data in addresses a20 to a0 we# ce#1 ce2 ub#, lb# d in dq15 to dq0 d out dq15 to dq0 t ds t wr t wp t cw high-z high-z t ch t dh t as t bw t be t coe t odw
november 7, 2002 am50dl128cg 57 preliminary flash erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 11 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. package pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. flash data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 56 sec byte program time 5 150 s excludes system level overhead (note 5) accelerated byte/word program time 4 120 s word program time 7 210 s chip program time (note 3) byte mode 42 126 sec word mode 28 84 description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 11 14 pf c out output capacitance v out = 0 12 16 pf c in2 control pin capacitance v in = 0 14 16 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
58 am50dl128cg november 7, 2002 preliminary psram data retention notes: 1. ce1#s v cc ? 0.2 v, ce2s v cc ? 0.2 v (ce1#s controlled) or ce2s 0.2 v (ce2s controlled). 2. typical values are not 100% tested. psram power on and deep power down figure 32. deep power-down timing figure 33. power-on timing parameter symbol parameter description test setup min typ max unit v dr v cc for data retention cs1#s v cc ? 0.2 v (note 1) 2.7 3.3 v i dr data retention current v cc = 3.0 v, ce1#s v cc ? 0.2 v (note 1) 1.0 (note 2) 100 a t cs ce2 setup time 0 ns t ch ce2 hold time 300 s t dpd ce2 pulse width 10 ms t chc ce2 hold from ce#1 0 ns t chp ce2 hold from power on 30 s ce#1 ce#2 t dpd t ch t cs ce#1 v dd ce#2 t chc t chp t ch v dd min
november 7, 2002 am50dl128cg 59 preliminary psram address skew figure 34. read address skew note: if multiple invalid address cycles shorter than t rc min occur for a period greater than 10 s, at least one valid address cycle over t rc min is required during that period. figure 35. write address skew note: if multiple invalid address cycles shorter than t wc min occur for a period greater than 10 s, at least one valid address cycle over t wc min , in addition to t wp min , is required during that period. ce#1 we# address t rc min over 10 s ce#1 we# address t wp min t wc min over 10 s
60 am50dl128cg november 7, 2002 preliminary physical dimensions fta088?88-ball fine-pitch grid array 11.6 x 8 mm 3237 \ 16-038.14b package fta 088 jedec n/a 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.40 profile a1 0.25 --- --- ball height a2 1.00 --- 1.11 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 88 ball count b 0.30 0.35 0.40 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a3,a4,a5,a6,a7,a8,b1,b10,c1,c10,d1,d10 depopulated solder balls e1,e10,f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10,m3,m4,m5,m6,m7,m8 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 index mark l m 88x ed corner c 0.15 (2x) (2x) c 0.15 e1 7 se b a d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view 6 b 0.20 c c 0.15 0.08 mc mc ab pin a1 7 d e pin a1 c top view side view corner a2 a1 a 0.08
november 7, 2002 am50dl128cg 61 preliminary revision summary revision a (september 30, 2002) initial release. revision a+1 (october 15, 2002) global replaced the 73-ball fbga package with the 88-ball fbga. pin description changed references from sram to psram added ry/by#2 and reset#2 revision a+2 (november 7, 2002) general description removed 8 m x 8-bit from product description. removed 8,388,608 bytes of 8 bits each from descrip- tion. mcp block diagram switched the #1 and #2 on reset# in diagram. removed v io f from diagram connection diagram added a 1 to the h2 pin (ce#f1). pin description removed a-1 and ciof from description and logic symbol. added a #1 and #2 to chip enable 1 and 2. table 1. device bus oper ations?flash word mode removed ciof = v ih from table title. table 2. device bus operat ions?flash byte mode, ciof = v il removed table, no byte mode offered on this mcp. global removed any references to byte mode from datasheet. table 3. am29dl640g sector architecture removed (x8) address range from table. flash command definitions changed last sentence of the first paragraph to ?....may place the device in an unknown state. a reset command is then required to return the device to read- ing array data.? table 7. cfi query identification string, table 8. system interface string, table 9. device geometry definition, and table 10. primary vendor-specific extended query removed addresses (byte mode) from tables. cmos compatible removed i acc parameter from table. added i lr parameter to table. table 12. am29dl640g command definitions changed the first address of the unlock bypass reset command sequence from ba to xxx. word/byte configuration, table 15. ciof timings for read operations, and table 17. ciof timings for write operations removed from datasheet. customer lockable: secsi sector not programmed or protect ed at the factory. added second bullet, secsi sector-protect verify text and figure 3. secsi sector flash memory region, and enter secsi sector/exit secsi sector command sequence noted that the acc function and unlock bypass modes are not available when the secsi sector is enabled. byte/word program command sequence, sector erase command sequence, and chip erase com- mand sequence noted that the secsi sector, autoselect, and cfi functions are unavailable when a program or erase operation is in progress.? common flash memory interface (cfi) changed wording in last sentence of third paragraph from, ?...the autoselect mode.? to ?...reading array data.? changed cfi website address. command definitions changed wording in last sentence of first paragraph from, ?...resets the device to reading array data.? to ...?may place the device to an unknown state. a reset command is then required to return the device to read- ing array data.?
62 am50dl128cg november 7, 2002 preliminary trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .

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